module ControlSignal_Multiplier(iClk,mul0,shiftright,Write);

input iClk, mul0;
output reg shiftright;
output Write;

reg Write00;

initial begin
shiftright=0;
Write00=0;
end

always @(negedge iClk) begin
shiftright=~shiftright;
end

always @(posedge iClk) begin
Write00=~Write00;
end

assign Write=Write00&mul0;

endmodule
